Aging-Aware Reliable Multiplier using Adaptive Hold Logic
Author(s):
Mohammad. Ajauddin, D.Sunil Suresh
Keywords:
Adaptive hold logic (AHL), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), reliable multiplier, variable latency.
Abstract
Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Mean while, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd),increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with16 ×16 column-bypassing multipliers can attain up to 62.88% performance improvement respectively compared with 16×16 fixed-latency column-by passing multipliers. Furthermore, our proposed architecture with 16 × 16 row-bypassing multipliers can achieve up to 80.17% performance improvement as compared with 16×16 fixed-latency row-bypassing multipliers.
Article Details
Unique Paper ID: 144101

Publication Volume & Issue: Volume 3, Issue 6

Page(s): 63 - 68
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