Design and Implementation of Zynq-Based Reconfigurable System for JPEG 2000 Compression
Mandapati Anil kumar, Y.Amar Babu
Zynq, JPEG Compression
This paper proposes design and implementation of area efficient Zynq-based self-reconfigurable system to perform jpeg 2000 compression, due to more complexity of jpeg 2000, hardware implementation on reconfigurable hardware fabric is needed. Here, we are proposed an embedded system named as zynq system which utilizes the filter bit streams for image compression. In the zynq there are two major parts processing system and programmable logic. The programmable logic means FPGA. FPGA is the reconfigurable system in which the compression filter bit streams are designed to perform jpeg 2000 compression. Here we used zynq-7010 ARM cortex- A9 series processor system, using Xilinx platform. The partial bit stream of 2-D DWT is created in SDK tool and then the FPGA is programmed for our required image compression. The results of accuracy and hardware components used are calculated.
Article Details
Unique Paper ID: 144830

Publication Volume & Issue: Volume 4, Issue 5

Page(s): 14 - 17
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Volume 5 Issue 7

Last Date 25 December 2018

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