FLOATING-POINT BUTTERFLY ARCHITECTURE BASED ON CARRY SELECT ADDER REPRESENTATION WITH IMPROVEMENT IN SPEED COMPUTATION
Author(s):
EASAM. SWAPNA PRIYA SINDHUJA, A.HARI PRASAD , P.ANIL KUMAR
Keywords:
Carry Select Adder (CSA) representation, butterfly unit, Fast Fourier Trans-form (FFT), Floating-Point (FP), three-operand addition.BSD (Binary significant digit) adder.
Abstract
Fast Fourier transform (FFT) coprocessor, having a significant impact on the performance of communication systems, and in DSP processors has been a hot topic of research in recent years. The FFT function is consists of consecutive multiply add operations over complex numbers, dubbed as butterfly units. Applying floating-point (FP) arithmetic to FFT architectures, specifically butterfly units, has become more popular recently. It offloads compute-intensive tasks from general-purpose processors by dismissing FP concerns (e.g., scaling and overflow/underflow). However, the major downside of FP butterfly is its slowness in comparison with its fixed-point counterpart. This reveals the incentive to develop a high-speed FP butterfly architecture to mitigate FP slowness. This brief proposes a fast FP butterfly unit using a devised FP fused-dot-product-add (FDPA) unit, to compute AB±CD±E, based on binary-signed-digit (BSD) representation. The FP three-operand BSD adder and the FP BSD constant multiplier are the constituents of the proposed FDPA unit. A carry-limited BSD adder is proposed and used in the three-operand adder and the parallel BSD multiplier so as to improve the speed of the FDPA unit. Moreover, modified Booth encoding technique is used to accelerate the BSD multiplier. The synthesis results show that the proposed FP butterfly architecture is faster than previous counterparts but requires more area.
Article Details
Unique Paper ID: 144850

Publication Volume & Issue: Volume 4, Issue 5

Page(s): 57 - 62
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Volume 4 Issue 5

Last Date 25 October 2017


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