Vernier Ring Oscillator Delay line based TDC using FPGA

Vernier Ring Oscillator Delay line based TDC using FPGA
Author(s):
Zalak Soni, Arpit Patel, Deepak Kumar Panda, Amit Basu Sarbadhikari
Keywords:
Time to Digital Converter (TDC), Field Programmable Gate Array (FPGA), Vernier Ring oscillator based Delay line, Low Resolution, Time of Flight (TOF) applications, Time interval measurement
Abstract
Power consumption, system stability and resolution of system are most important factors in time interval measurement. Time interval measurement is needed in many TOF (time of flight) applications e.g. TOF mass spectrometer and TOF particle detector. In this paper, vernier delay line with ring oscillators based TDC (Time to digital converter) is presented for time interval measurement between two pulses. To achieve low power this algorithm is implemented on Actel Flash based FPGA. This delay line mainly comprises of two oscillators with slight difference in their frequencies, phase detector and two counters. Manual placement of the critical elements needs to be done in order to improve resolution of the system. Circuit of oscillators phase detector, design flow and timing simulation (post-layout simulation) results of implemented delay line are discussed in this paper.
Article Details
Unique Paper ID: 144909 Publication Volume & Issue: Volume 4, Issue 6 Page(s): 96 - 99
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