OPTIMIZED ERROR DETECTION FOR RESIDUE ADDER USING SIGNED DIGIT ARITHMETIC

OPTIMIZED ERROR DETECTION FOR RESIDUE ADDER USING SIGNED DIGIT ARITHMETIC
Author(s):
G.CHANDANA , P.RAJANI
Keywords:
Residue Adder, Error Detection
Abstract
In this paper, a new residue checker using optimal signed-digit (SD) adder tree structure is presented for the error detection of multiply-accumulate arithmetic circuit. The modulus of the redisue cheker is set to m = 2p + u, where u ∈ {−1, 1}and p is the word length of the residue checker. By switching u = 1 to/from u = −1, more 2-bit errors can be detected using the same checking circuit. The fast modulo m SD adder with an end-around carry is introduced, so that the modulo m addition time is independent of the word length of operands of the residue checker, and the delay time of the proposed residue checker is dependent of the stages of the binary tree structure of the modulo-m SD adders.
Article Details
Unique Paper ID: 145077 Publication Volume & Issue: Volume 4, Issue 7 Page(s): 258 - 260
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