Low Power Area Efficient Full Adder Cell New Approach Using GDI Technique

Low Power Area Efficient Full Adder Cell New Approach Using GDI Technique
Author(s):
Veerraju kaki
Keywords:
Complementary Metal Oxide Semiconductor (CMOS), Digital Signal Processing (DSP), Gate Diffusion Input (GDI), Very Large Scale Integration (VLSI), Exclusive OR gate (XOR).
Abstract
An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors. An adder determines the overall performance of the circuits in most of those systems. In this paper proposed a low power 1-bit full adder cell with less number of transistors. The power dissipation and area using the new design are analysed and compared with those of other designs using tanner tool. The results show that the proposed adder has both lower power consumption and less area.
Article Details
Unique Paper ID: 145207 Publication Volume & Issue: Volume 4, Issue 7 Page(s): 722 - 725
Article Preview & Download

Share This Article

NCSEM 2024

National Conference on Sustainable Engineering and Management - 2024

Last Date: 15th March 2024

IJIRT.org enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on editor@ijirt.org