Efficient Pipelined CORDIC Architecture for Generation of Sine and Cosine Function

Efficient Pipelined CORDIC Architecture for Generation of Sine and Cosine Function
Author(s):
Ravi Mogili, Raju Katru, Kandukuri Shobha
Keywords:
FPGA, CORDIC Algorithm, Folded & Unfolded Architecture, serial and parallel pipelined CORDIC, sine and cosine functions.
Abstract
In processing the real world data Digital signal processing algorithms provide unbeatable efficiency. One of the DSP algorithms is COordinate Rotation DIgital computer (CORDIC). The beauty of CORDIC lies in the fact that by simple shift-add operations and theCORDIC has gained momentum for decades because of its less hardware complexity. CORDIC algorithm isvery simple and iterative process for performing various mathematical computations. Most of the literaturelacks in calculation of resources utilized by a particular CORDIC architecture. In this paper, serial, paralleland pipelined CORDIC architecture has been implemented for computing both sine & cosine functions.This paper makes an attempt to survey different forms of CORDIC algorithms and its architectures and applications explore implementation exact to FPGAs and the way the structure has been coded in VERILOG, synthesis evaluation are carried out making use of Xilinx ISim software and targeted on Xilinx FPGA synthesis device.
Article Details
Unique Paper ID: 145250 Publication Volume & Issue: Volume 4, Issue 8 Page(s): 447 - 452
Article Preview & Download

Share This Article

NCSEM 2024

National Conference on Sustainable Engineering and Management - 2024

Last Date: 15th March 2024

IJIRT.org enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on editor@ijirt.org