Design and Implementation of Pipelined AES Algorithm on FPGA
Author(s):
Roopa Rao, Amaresha S.K
Keywords:
AES, Composite Field, FPGA, Galois Field, Key expansion,pipelined S-Box, Rijndael.
Abstract
The paper presents high speed architecture for the hardware implementation of the Advanced Encryption Standard (AES) Algorithm. The proposed design employs a Galois Field, GF(28), SubBytes (S-Box) transformation based on Rijndael algorithm in the Field Programmable Gate Arrays (FPGAs). The implementation of S-Box carried out by two stages pipelining for the small area occupancy and high throughput. In addition key expansion architecture suitable for the pipelined AES also presented. The design is implemented and synthesized using Xilinx ISE v13.4 and Xilinx Spartan-3E XC3S2500E-4 as a target device. The timing results from the Place and Route report indicate that area occupied by this architecture is 67% of the slices.
Article Details
Unique Paper ID: 145254

Publication Volume & Issue: Volume 4, Issue 8

Page(s): 149 - 155
Article Preview & Download




Go To Issue



Call For Paper

Volume 5 Issue 1

Last Date 25 June 2018


About Us

IJIRT.org enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on editor@ijirt.org

Social Media

Contact Details

Telephone:704 821 9842/43
Email: editor@ijirt.org
Website: ijirt.org