Optimization of Full adder cells Using HDL
Author(s):
J.Mallikarjunarao, P.Srinivas, S.Ramakoteswara Rao, B.Ramarao
Keywords:
Adder, Low power, Multiplexer, RCA adder
Abstract
Power consumption has emerged as a primary design constraint for integrated circuits (ICs). In the Nanometer technology regime, leakage power has become a major component of total power [1]. Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU, and the power consumption of an ALU can be lowered by lowering the power consumption of Full adder. So the full adder designs with low power characteristics are becoming more popular these days. In this paper we are going to design four different types of Full adder these are applied to 32-bit RCA .The four designs will be developed using Verilog HDL.
Article Details
Unique Paper ID: 145256

Publication Volume & Issue: Volume 4, Issue 8

Page(s): 156 - 160
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Volume 4 Issue 8

Last Date 25 January 2018


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