DESIGN AND SIMULATION OF 2-BIT FULL SUB TRACTOR AT 32 nm CMOS TECHNOLOGIES
Author(s):
M.M. Prasada Reddy
Keywords:
CMOS, VLSI, Full Subtractor, Power consumption, CMOS technology
Abstract
Low power and efficient area are frequently required in very large scale integration design. The Complementary Metal Oxide Semiconductor (CMOS) are used in various electronic fields viz manufacturing of digital integrated circuits, microcontrollers and microprocessors. In this paper, the proposed CMOS 2- bit full Subtractor is simulated and analyzed using Microwind 3.1at 32nm CMOS technologies. The full Subtractor is sowing good performance in terms of power dissipation and area.
Article Details
Unique Paper ID: 146303

Publication Volume & Issue: Volume 4, Issue 12

Page(s): 131 - 133
Article Preview & Download




Go To Issue



Call For Paper

Volume 5 Issue 4

Last Date 25 September 2018


About Us

IJIRT.org enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on editor@ijirt.org

Social Media

Contact Details

Telephone:704 821 9842/43
Email: editor@ijirt.org
Website: ijirt.org