Radix-2 FFT Bit Reversal Architecture to Process double Data Streams for MIMO

Radix-2 FFT Bit Reversal Architecture to Process double Data Streams for MIMO
Author(s):
S.PRASANNA DEVI, G.KAVITHA
Keywords:
Bit-reversal circuit, fast Fourier transform (FFT), MDC, MDF, natural-order FFT output.
Abstract
Bit-reversal is an essential part of the fast Fourier transform. However, compared to the amount of works on FFT architectures, much fewer works are dedicated to bit-reversal circuits until recent years. In this brief, the minimum latency and memory required for calculating the bit-reversal of continuous-flow parallel data are formulated. The proposed circuit is simple and efficient for reordering the output samples of parallel pipelined FFT processors. The proposed approach can be Implemented using Verilog HDL and Simulated by Modelsim 6.4 c. Finally it‟s synthesized by Xilinx tool.
Article Details
Unique Paper ID: 146388 Publication Volume & Issue: Volume 4, Issue 12 Page(s): 524 - 534
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