Design of Higher Order FIR Filter for Different Techniques of Multiplication
Author(s):
Gaurav Gautam, Prashant K Shah
Keywords:
Adder; Multiplier; Filter; CSD(canonic sign digit); RCA(ripple carry adder); Xilinx.
Abstract
Today’s DSP systems are well suited to VLSI implementation and if implemented using VLSI technologies they are often economically viable or technically feasible. The focus of this paper is to the design an FIR filter with efficient VLSI architecture to reduce the power consumption and the hardware complexity to optimize the filter area, delay and power. Basically optimization of”filter’area, delay and power is done by using add & shift method for.multiplication, but here power dissipation of’the’filter will increase. Complexity of the filter can be reduced by representing the coefficients in canonical signed digit’(CSD) representation as it is more efficient than the traditional”binary representation. In this paper, we will see different multiplication techniques for filter design such as, add and shift method, Vedic multiplier, Booth Multiplier and Wallace tree’(WT) multiplier for the multiplication of'filter coefficients with filter input. MATLAB is used for designing of Finite Impulse Response (FIR) filter using the equiripple‘method and the same filter is synthesized on Xilinx Spartan3E target field-programmable gate array(FPGA) device using Hardware Description Language(HDL) and the total on-chip’power is calculated in Vivado. After simulation results comparison for all the filter structures, it is shown that the best-optimized filter among all is FIR filter using WT multiplier.
Article Details
Unique Paper ID: 146674

Publication Volume & Issue: Volume 5, Issue 1

Page(s): 520 - 526
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