DESIGN HIGH SPEED LOW POWER COMBINATIONAL AND SEQUENTIAL CIRCUITS USING REVERSIBLE DECODER
Author(s):
RAJITHA ORCHU, RSVS ARAVIND
ISSN:
2349-6002
Cite This Article:
DESIGN HIGH SPEED LOW POWER COMBINATIONAL AND SEQUENTIAL CIRCUITS USING REVERSIBLE DECODERInternational Journal of Innovative Research in Technology(www.ijirt.org) ,ISSN: 2349-6002 ,Volume 6 ,Issue 6 ,Page(s):159-163 ,November 2019 ,Available :IJIRT148807_PAPER.pdf
Keywords:
Reversible logic, quantum cost, garbage outputs.
Abstract
Reversible logic has presented itself as a prominent technology which plays an imperative role in Quantum Computing. Quantum computing devices theoretically operate at ultra-high speed and consume infinitesimally less power. Research did in this project aims to utilize the idea of reversible logic to break the conventional speed-power trade-off, thereby getting a step closer to realize Quantum computing devices. To authenticate this research, various combinational and sequential circuits are implemented such as N-bit Ripple-carry Adder/subtract or, comparator D-flip flop and ring counter using Reversible gates. The power and speed parameters for the circuits have been indicated, and compared with their conventional non-reversible counterparts. The comparative statistical study proves that circuits employing Reversible logic thus are faster and power efficient.
Article Details
Unique Paper ID: 148807

Publication Volume & Issue: Volume 6, Issue 6

Page(s): 159 - 163
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Last Date 25 December 2019


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