Optimization Of CMOS Low Power High Speed Dual Edge Triggered Flip Flop

  • Unique Paper ID: 100021
  • Volume: 1
  • Issue: 1
  • PageNo: 0-0
  • Abstract:
  • No Abstract Found
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Copyright © 2025 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

BibTeX

@article{100021,
        author = {Harpreet Singh},
        title = {Optimization Of CMOS Low Power High Speed Dual Edge Triggered Flip Flop },
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {1},
        number = {1},
        pages = {0-0},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=100021},
        abstract = {},
        keywords = {},
        month = {},
        }

Cite This Article

  • ISSN: 2349-6002
  • Volume: 1
  • Issue: 1
  • PageNo: 0-0

Optimization Of CMOS Low Power High Speed Dual Edge Triggered Flip Flop

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