Design and Implementation of High Speed Digital Vedic Multiplier using Cadence

Design and Implementation of High Speed Digital Vedic Multiplier using Cadence
Author(s):
Gururaj.Panghri, Dr.P.Venkataratnam, Dr Siva Yellampalli
Keywords:
Verilog, Vedic Mathematics, Ancient, Crosswise
Abstract
In this design our objective is to emphasize the importance of Vedic Mathematics for digital applications. Ancient Vedic mathematics not only facilitate the complex mathematical Operations but also useful for logical applications. In the present work we are using the concept of Urdhva-tiryakbyham, i.e., vertical and crosswise Multiplication and its implementation for 16-bit multiplication. This technique optimizes the output in term of steps of calculation and therefore reduces the delay, area, power of a digital circuit. We develop this design with the help of front end language Verilog.
Article Details
Unique Paper ID: 144952 Publication Volume & Issue: Volume 4, Issue 6 Page(s): 222 - 224
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