Microcontroller Based Testing of Digital IP-Core

Shubham Gupta; Shripad G. Desai

Microcontroller Based Testing of Digital IP-Core

Authors: Shubham Gupta , Shripad G. Desai

Unique Paper ID: 150565
Volume: 7
Issue: 7
PageNo: 231-236

Keywords: No Keywords Found

Abstract:
Testing core-based System on Chip [1] is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. At speed testing using external testers is more expensive because of gigahertz processor. The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores [2]. The prominent feature of the approach is to use microcontroller to test IP-core. The novel feature is that there is no need of test pattern generator and output response analyzer as microcontroller performs the function of both. This approach has various advantages such as at speed testing, low cost, less area overhead and greater flexibility since most of the testing process is based on software.

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Cite This Article

ISSN: 2349-6002
Volume: 7
Issue: 7
PageNo: 231-236

Microcontroller Based Testing of Digital IP-Core

Available:https://ijirt.org/Article?manuscript=150565

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