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@article{207126,
        author = {Suroju Sai Santhosh Kumar and Udutha Saritha},
        title = {Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {2},
        pages = {3981-3985},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=207126},
        abstract = {A Low-power and noise-immune domino logic architecture is designed and synthesized in the 7-nm predictive technology (FinFET) model. The proposed circuit includes a keeper transistor, clock controlled footer devices, a stacking mechanism and a semi-dynamic output stage to minimize the leakage current and to avoid the possibility of false switching at the dynamic node. To validate the proposed technique a 2-input domino OR gate is used since its parallel pull-down network is a critical leakage condition without inherent transistor stacking. Simulations are done in Cadence Spectre on a nominal 0.8 V supply, a temperature of 27 °C, a clock frequency of 10 GHz and an output load of 10 fF. The proposed design consumes 0.33 nW as compared to the already existing domino logic structures, which consumes 15% less power than the existing ones and it has nearly 10% better speed.},
        keywords = {Domino logic, Low Power, Noise Immunity, Dynamic node, OR.},
        month = {July},
        }