Design of ring VCO based PLL using 0.25 痠 CMOS technology

Design of ring VCO based PLL using 0.25 痠 CMOS technology
Author(s):
Ritika Tiwari, Vijay Sharma, Megha Soni
Keywords:
Phase Locked Loop, Injection Locking, Ring VCO, Shift Bias Level.
Abstract
A low power ring VCO based PLL using injection locking is realized by adopting 0.25繕m CMOS technology at 2.5V. We have achieved a shift in the bias level by using pMOS active resistive load. The PLL output frequency is 104.4 MHz, at 5 MHz reference frequency by using injection locking based VCO and active resistive load managed to achieve low power dissipation of 4.98mW at 2.5 V.
Article Details
Unique Paper ID: 143290 Publication Volume & Issue: Volume 2, Issue 9 Page(s): 52 - 56
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