Novel Shared Multiplier Scheduling Scheme For Area-Efficient FFT/IFFT Processors
Author(s):
S.V.V.Sudhakar, R.Radha Kumari
Keywords:
Fast Fourier transform (FFT), mixed-radix multipath delay commutator (MRMDC)
Abstract
This paper based on a new shared multiplier scheduling scheme (SMSS) for area-efficient fast Fourier transform (FFT)/inverse FFT processors. SMSS can significantly reduce the total number of complex multipliers up to 28%. The proposed mixed-radix multipath delay commutator processors can support128/256 and 256/512-point FFTs using SMSS. The proposed processors have been designed and implemented with 90-nm CMOS technology, which can reduce the total hardware complexity by 20%. The proposed processors having eight-parallel data paths can achieve a high throughput rate up to 27.5 GS/s at 430 MHz. In addition, the proposed processors can support any FFT size using additional stages
Article Details
Unique Paper ID: 145320

Publication Volume & Issue: Volume 4, Issue 9

Page(s): 24 - 31
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Last Date 25 September 2018


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