Transmission of High Bandwidth Data and Images with Integrated real-time Data Densification using a Scalable Network Model

  • Unique Paper ID: 175014
  • Volume: 3
  • Issue: 7
  • PageNo: 229-235
  • Abstract:
  • Our civilization is increasingly reliant on the transmission and receipt of massive volumes of data across serial connections with ever-increasing bit rates. Even when contemporary serial buses with high data rates are utilized, the frame rate possible in imaging systems is frequently restricted by the serial link between a camera and a host. This article describes a scalable connection system with a bandwidth and interface standard that can be readily customized to fit a specific application. The scalable serial connection technique has been enhanced with lossless data compression, with the goal of boosting dataflow at a fixed bit rate. The compression mechanism is included into the scalable transceivers, giving a complete solution for effective data transfer over a range of interfaces. The system is entirely constructed on an FPGA, utilizing a totally hardware-based architecture. The system was implemented and tested using a Terasic DE4 board, with Quartus-II software and design and debugging tools. The impact of compressing the image and conveying the compressed data over parallel lines is comparable to that of compressing the same image within a single core with a greater compression ratio, which in this system ranges between 7.5 and 126.8.

Copyright & License

Copyright © 2025 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

BibTeX

@article{175014,
        author = {Rekha P, Vishalakshi V, Chamaraju Y S and Vishalakshi V and Chamaraju Y S},
        title = {Transmission of High Bandwidth Data and Images with Integrated real-time Data Densification using a Scalable Network Model},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {3},
        number = {7},
        pages = {229-235},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=175014},
        abstract = {Our civilization is increasingly reliant on the transmission and receipt of massive volumes of data across serial connections with ever-increasing bit rates. Even when contemporary serial buses with high data rates are utilized, the frame rate possible in imaging systems is frequently restricted by the serial link between a camera and a host. This article describes a scalable connection system with a bandwidth and interface standard that can be readily customized to fit a specific application. The scalable serial connection technique has been enhanced with lossless data compression, with the goal of boosting dataflow at a fixed bit rate. The compression mechanism is included into the scalable transceivers, giving a complete solution for effective data transfer over a range of interfaces. The system is entirely constructed on an FPGA, utilizing a totally hardware-based architecture. The system was implemented and tested using a Terasic DE4 board, with Quartus-II software and design and debugging tools. The impact of compressing the image and conveying the compressed data over parallel lines is comparable to that of compressing the same image within a single core with a greater compression ratio, which in this system ranges between 7.5 and 126.8.},
        keywords = {Bandwidth, Scalable network, Real-time data, Images, Serial buses.},
        month = {April},
        }

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