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@article{208212,
        author = {Ms. Sneha J. Kharate and Dr. Swati S. Shetkar},
        title = {A Comprehensive Review of High-Speed Array Multipliers Using 4:2 Compressors},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {4},
        pages = {900-903},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=208212},
        abstract = {Multipliers are fundamental arithmetic units widely used in digital signal processing, microprocessors, image processing, convolution, filtering, cryptography, and VLSI systems. The performance of a multiplier directly influences the overall speed, power consumption, and area of arithmetic-intensive digital systems. This review paper presents a comprehensive study of array multipliers and compressor-based multiplier architectures, with particular emphasis on the application of 4:2 compressors for partial-product reduction. The review examines the operating principles, architectural structures, and performance characteristics of conventional array multipliers and compressor-based designs. Different 4:2 compressor implementations, including logic-gate-based, multiplexer-based, and transistor-level approaches, are discussed and compared in terms of propagation delay, power dissipation, silicon area, Power-Delay Product (PDP), and Area-Delay Product (ADP). Reported results from existing studies indicate that incorporating compressors into the partial-product reduction stage can substantially reduce the number of addition levels and improve multiplier performance.},
        keywords = {Array Multiplier, 4:2 Compressor, Partial Product Reduction, VLSI, Low-Power Design, High-Speed Arithmetic, Power-Delay Product (PDP), Area-Delay Product (ADP).},
        month = {September},
        }