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@article{204331,
        author = {Ashritha Vashista H.A. and Dr.M.C.Chandrashekhar},
        title = {A Review of Monolithic 3D Acceleration of SRAM using Planar MOSFETs for Low Power and Reliability},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {1},
        pages = {1760-1763},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=204331},
        abstract = {This review paper presents a comprehensive survey of Monolithic 3D (M3D) integration techniques applied to 8 transistor (8T) SRAM cells designed with planar MOSFETs, with a focus on achieving low power consumption and high reliability [1]. Conventional 6T SRAM architectures face significant stability limitations—most notably the read disturb phenomenon—during high speed memory operations. This paper examines the existing body of literature concerning 8T SRAM bit cell topologies implemented in 90 nm planar CMOS technology, wherein the read path is effectively decoupled from the internal storage nodes. The review synthesizes key findings related to Static Noise Margin (SNM) enhancement, Power Delay Product (PDP) reduction, and the advantages conferred by monolithic 3D stacking compared to traditional through silicon via (TSV) based 3D integration [2]. This work establishes the theoretical benchmarks and design considerations that will inform subsequent simulation based validation of the proposed 8T SRAM architecture.},
        keywords = {Monolithic 3D (M3D), 8T SRAM, Planar MOSFET, Low Power, Reliability, 90nm CMOS.},
        month = {June},
        }