Author Login IJIRT Partner Network (IPN) Login

DESIGN OF CACHE CONTROLLER FOR LOW POWER AND HIGH SPEED APPLICATION BY USING CACHE MEMORY

  • Unique Paper ID: 147683
  • Volume: 5
  • Issue: 10
  • PageNo: 269-271
  • Abstract:
  • We report on the design of efficient cache Controller suitable for Cache Memory use in FPGA-based processors. Cache systems are on-chip memory elements used to store data that are frequently referenced by programs. The advantage of storing data in cache, as compared to RAM, is that it has faster retrieval times, but it has the disadvantage of on-chip energy consumption. A cache-decay interval is the amount of time a cache element holds unreferenced data before being turned off (cleared). Semiconductor memory which can operate at speeds comparable with the operation of the processor exists; it is not economical to provide all the main memory with very high speed semiconductor memory. The problem can be alleviated by introducing a small block of high speed memory called a cache between the main memory and the processor.
Download article email to a friend

Cite This Article

  • ISSN: 2349-6002
  • Volume: 5
  • Issue: 10
  • PageNo: 269-271

DESIGN OF CACHE CONTROLLER FOR LOW POWER AND HIGH SPEED APPLICATION BY USING CACHE MEMORY

Related Articles

24 Apr, 2020

Sun Tracking Solar Panel Efficiency Enhance by Using Microcontroller

Read More
Impact Factor
8.01 (Year 2024)
UGC Approved
Journal no 47859

Join Our IPN

IJIRT Partner Network

Submit your research paper and those of your network (friends, colleagues, or peers) through your IPN account, and receive 800 INR for each paper that gets published.

Join Now

Latest Publication

Archive

View More

Recent Conferences

NCSEM 2024

National Conference on Sustainable Engineering and Management - 2024 Last Date: 15th March 2024

Submit inquiry