| DESIGN OF CACHE CONTROLLER FOR LOW POWER AND HIGH SPEED APPLICATION BY USING CACHE MEMORY |
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| Author(s): |
| Parag G shewane, Ms. Amruta G Shewane, Mr. Ritesh C. Ujawane, Mr. Sagar A Patil, Bhagyashree G. Mudaliar |
| ISSN: |
| 2349-6002 |
| Cite This Article: |
DESIGN OF CACHE CONTROLLER FOR LOW POWER AND HIGH SPEED APPLICATION BY USING CACHE MEMORY, International Journal of Innovative Research in Technology(www.ijirt.org) ,ISSN: 2349-6002 ,Volume 5 ,Issue 10 ,Page(s):269-271 ,March 2019 ,Available :IJIRT147683_PAPER.pdf |
| Keywords: |
| Cache Memory, Main Memory, Cache Controller |
| Abstract |
| We report on the design of efficient cache Controller suitable for Cache Memory use in FPGA-based processors. Cache systems are on-chip memory elements used to store data that are frequently referenced by programs. The advantage of storing data in cache, as compared to RAM, is that it has faster retrieval times, but it has the disadvantage of on-chip energy consumption. A cache-decay interval is the amount of time a cache element holds unreferenced data before being turned off (cleared). Semiconductor memory which can operate at speeds comparable with the operation of the processor exists; it is not economical to provide all the main memory with very high speed semiconductor memory. The problem can be alleviated by introducing a small block of high speed memory called a cache between the main memory and the processor. |
| Article Details |
| Unique Paper ID: 147683 Publication Volume & Issue: Volume 5, Issue 10 Page(s): 269 - 271 |
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