Design and Implementation of Run-time reconfigurable multi-precision FP multiplier

Design and Implementation of Run-time reconfigurable multi-precision FP multiplier
Author(s):
M V Sarala Rani, Pradeep S V, Dr Siva Yellampalli
Keywords:
FP, Multiplier
Abstract
Floating Point (FP) multiplication is used based on the need of the application and this work has showed the reconfigurable FP multiplier with six different modes. The different modes give different precision as the modes are divided based on the number of mantissa bits. The complex part of FP multiplication is the Mantissa multiplication that is done with the efficient use of both the Karatsuba and Urdhva algorithm. Here, we had targeted for the decrease in the delay and area and it has been achieved successfully with usage of simple carry select and save adders instead of the ripple carry adders. The fully fledged Double precision multiplier actually consumes more area and also delay is more, here we have reduced the delay by 47 percent approximately in comparison to the reference.
Article Details
Unique Paper ID: 144666 Publication Volume & Issue: Volume 4, Issue 2 Page(s): 29 - 34
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