Implementation of Fast Counting L2 Cache Architecture Using Bloom Filter
S. Sathyadeepa, T. Sasikala, B. Suresh
Computer architecture, counting bloom filters, Implementation, low power, microprocessors.
Many high-performance microprocessors employ cache write-through policy for performance improvement. However, write-through policy also incurs large energy overhead due to the increased accesses to caches at the L2 caches. To overcome this problem we use way tagged cache. In the exiting work, we present novel ideas for both cache hit and miss predictions. Partial tag enhanced bloom filter to reduce the tag comparisons of the cache hit prediction method. In the proposed technique enables CBFs(counting bloom filters)to improve upon the energy, delay, and complexity of various processor structure when compared with exiting work. This paper studies the energy, delay, and area characteristics of two implementations for CBFs using full custom layouts in a commercial 0.13- m fabrication technology. One implementation is S-CBF, other implementation is L-CBF. Our results demonstrate that for a variety of L-CBF organizations, the estimations by analytical models are within 5% and 10% of spectra simulation results
Article Details
Unique Paper ID: 147184

Publication Volume & Issue: Volume 5, Issue 5

Page(s): 170 - 176
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Last Date 25 August 2020

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