|UART Transmitter Experiment in FPGA|
|Dr. S. S. Limaye, Dr. Hema Kale|
|Cite This Article:|
UART Transmitter Experiment in FPGA, International Journal of Innovative Research in Technology(www.ijirt.org) ,ISSN: 2349-6002 ,Volume 6 ,Issue 1 ,Page(s):392-395 ,June 2019 ,Available :IJIRT148349_PAPER.pdf
|UART, DIP, VHDL, FPGA, SDO, ISE|
|Universal Asynchronous Receiver Transmitter (UART) is a very commonly used device in microprocessors. But implementing it in VHDL is not an easy task for students. This paper proposes a simple way of implementation by using set-ups available in the college labs. From faculty point of view, it will help them to encourage lab research in VHDL for exploring students’ knowledge. Here UART is developed using FPGA. The specifications are: UART should continuously read a byte from the DIP switches and serially transmit it on the SDO (Serial Data Output) line as long as a pushbutton is pressed and the baud rate should be maintained constant as specified. Testing is done in two parts, first simulation of the circuit is carried out using Xilinx ISE package and then Hardware testing is done on Spartan III FPGA kit (Basys)|
|Unique Paper ID: 148349|
Publication Volume & Issue: Volume 6, Issue 1
Page(s): 392 - 395
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