AN EFFICIENT DECODING ARCHITECTURE WITH IMPROVED ERROR CORRECTING TECHNIQUE FOR NB-LDPC CODE
Author(s):
SAALINI SV, NIVEDHA N, Kamalakannan S
Keywords:
Abstract
Due to higher integration densities, technology scaling and variation in parameters, the performance failures may occur for every application. The memory applications are also prone to single event upsets and transient errors which may lead to malfunctions. This paper proposed a novel error detection and correction method using EG-LDPC. This is useful as majority logic decoding can be implemented serially with simple hardware but requires a large decoding time. For memory applications, this increases the memory access time. The method detects whether a word has errors in the first iterations of majority logic decoding, and when there are no errors the decoding ends without completing the rest of the iterations. Also, errors affecting more than five bits were detected with a probability very close to one. The probability of undetected errors was also found to decrease as the code block length increased. For a billion error patterns only a few errors (or sometimes none) were undetected. This may be sufficient for some applications. Error commonly occurs in the Flash memory while employing LDPC decoding. The SRMMU actually suggests to use a the VTVI design by introducing the Context Number register, however also a PTPI or VTPI design could be implemented that complies to the SRMMU standard. The VTVI design with a physical write buffer and a combined I/D Cache TLB is the simplest design to implement. This will give error correction in minimum cyclic period using LDPC method.
Article Details
Unique Paper ID: 149441

Publication Volume & Issue: Volume 6, Issue 12

Page(s): 377 - 383
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Last Date 25 June 2020


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