Implementation of Low Power and Area Efficient Vedic Multiplier Using FinFET based Pass Transistor Logic
M.Sahira, M.Santhiya, G.Sathya Priya, K.Valuppural, T.Mani
Arithmetic operation,Algebra,FinFET,Vedic Multiplier
Designing a low power consuming and area efficient Vedic multiplier using Hybrid Full Adder. Arithmetic operations plays on vital role in many real-time applications. Vedic multiplier has been introduced to solve the problems of existing multiplier. High speed and low power multiplier has been in increasing demand day by day. Multiplier like Array multiplier, Booth multiplier, Bit serial multiplier, Carry save multiplier and etc.., are used for as source of the algorithms. This algebra arithmetic operations and geometry. Urdhva Tiryabhyam is widely employed formula which provides high speed and efficient. This paper design a Vedic multiplier with FinFET based pass transistor logic.2*2 and 4*4 Vedic multipliers are developed and executed 180nm approach with Tanner EDA Tool 3.0.
Article Details
Unique Paper ID: 151426

Publication Volume & Issue: Volume 7, Issue 12

Page(s): 679 - 683
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Last Date 25 September 2021

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