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CMOS Implementation of Low Complexity Multiplication Technique

  • Unique Paper ID: 142432
  • Volume: 2
  • Issue: 1
  • PageNo: 336-338
  • Abstract:
  • A low-complexity design for multiplication is primary requirement in Fast Fourier implementation. In this work an optimized multiplier for twiddle factor multiplier is designed. The proposed multiplier is slightly modified from the existing complex multipliers. A 3 bit multiplier is designed which results low power consumption with high speed. The presented complex multiplier with minimum complexity has with much less delay and simulation time, which reduces overall speed when implemented in FFT. The proposed CMOS implementation of multiplier is simulated in 45 nm scale using tanner tool version 14.11.
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Cite This Article

  • ISSN: 2349-6002
  • Volume: 2
  • Issue: 1
  • PageNo: 336-338

CMOS Implementation of Low Complexity Multiplication Technique

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