A low-complexity design for multiplication is primary requirement in Fast Fourier implementation. In this work an optimized multiplier for twiddle factor multiplier is designed. The proposed multiplier is slightly modified from the existing complex multipliers. A 3 bit multiplier is designed which results low power consumption with high speed. The presented complex multiplier with minimum complexity has with much less delay and simulation time, which reduces overall speed when implemented in FFT. The proposed CMOS implementation of multiplier is simulated in 45 nm scale using tanner tool version 14.11.
Article Details
Unique Paper ID: 142432
Publication Volume & Issue: Volume 2, Issue 1
Page(s): 336 - 338
Article Preview & Download
Share This Article
Conference Alert
NCSST-2023
AICTE Sponsored National Conference on Smart Systems and Technologies
Last Date: 25th November 2023
SWEC- Management
LATEST INNOVATION’S AND FUTURE TRENDS IN MANAGEMENT