TO DESIGN HIGH SPEED AND LOW POWER ALU USING VEDIC MATHEMATICS
Author(s):
Sachin V
Keywords:
DSP, Arithmetic Logical Unit, Adder, Multiplication, Vedic Urdhva Tiryagbhyam multiplication algorithm, Vedic Multiplier (VM)
Abstract
Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculation based on formula (sutras). It deals with various branches of mathematics like arithmetic, algebra, geometry etc. The speed of arithmetic calculation is of extreme importance and depends greatly on the speed of multiplier. Urdhva Tiryagbhyam Vedic method for multiplication, strikes a difference of actual process of multiplication, by enabling parallel generation of intermediate product, eliminating unwanted multiplication steps with zeros and scaled to higher bit level. This formula (Sutras) is used to build high speed power efficient multiplier in coprocessor. This project is to design arithmetic module using the technique of ancient Indian Vedic Mathematics to improve the performance of coprocessor. This project is to design NxN arithmetic modules, where A & B are the two N bits inputs of these module and different sections of module are multiplier which is designed by using Vedic algorithm of multiplication named Urdhva Tiryagbhyam multiplier and with carry save adder, adder/ subtractor and MAC unit.
Article Details
Unique Paper ID: 143816

Publication Volume & Issue: Volume 3, Issue 2

Page(s): 95 - 98
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