HIGH SPEED LOW POWER PERFORMANCE OF 8-BIT PARALLEL MULTIPLIER ACCUMULATOR USING MODIFIED RADIX-8 BOOTH ALGORITHM

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ISSN: 2349-6002 ESTD Year: 2014

UGC approved journal no 47859

HIGH SPEED LOW POWER PERFORMANCE OF 8-BIT PARALLEL MULTIPLIER ACCUMULATOR USING MODIFIED RADIX-8 BOOTH ALGORITHM
Author(s):
SREEKANTH BAIRAGONI, VINAYKUMAR ANKIREDDY
Keywords:
FPGA, MAC, Booth Algorithm, LUT, Booth Multiplier, Booth Encoder, Booth Decoder, CSA.
Abstract
This paper proposes a new architecture of multiplier-and-accumulator (MAC) for high speed and low-power by adopting the new SPST implementing approach. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation In this we used Modelsim for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification on targeted FPGA.
Article Details
Unique Paper ID: 144114 Publication Volume & Issue: Volume 3, Issue 6 Page(s): 116 - 120
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