HIGH SPEED LOW POWER PERFORMANCE OF 8-BIT PARALLEL MULTIPLIER ACCUMULATOR USING MODIFIED RADIX-8 BOOTH ALGORITHM

HIGH SPEED LOW POWER PERFORMANCE OF 8-BIT PARALLEL MULTIPLIER ACCUMULATOR USING MODIFIED RADIX-8 BOOTH ALGORITHM
Author(s):
SREEKANTH BAIRAGONI, VINAYKUMAR ANKIREDDY
Keywords:
FPGA, MAC, Booth Algorithm, LUT, Booth Multiplier, Booth Encoder, Booth Decoder, CSA.
Abstract
This paper proposes a new architecture of multiplier-and-accumulator (MAC) for high speed and low-power by adopting the new SPST implementing approach. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation In this we used Modelsim for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification on targeted FPGA.
Article Details
Unique Paper ID: 144114 Publication Volume & Issue: Volume 3, Issue 6 Page(s): 116 - 120
Article Preview & Download

Share This Article

NCSEM 2024

National Conference on Sustainable Engineering and Management - 2024

Last Date: 15th March 2024

IJIRT.org enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on editor@ijirt.org