Simulation of BIST based Multiplier using FPGA

G.Sathwik; Syed Mohammed Ali

Simulation of BIST based Multiplier using FPGA

Authors: G.Sathwik, Syed Mohammed Ali

Unique Paper ID: 145466
Volume: 4
Issue: 10
PageNo: 973-979

Keywords: No Keywords Found

Abstract:
The ever increasing applications of integrated circuits in the day-to-day useful electronic gadgets is the driving force for the development of low power designs of configurable hardware designs. High speed and low power are the main parameters that are targeted by modern circuit designers. Multipliers are the very important logic operational unit of any processing unit in digital signal processing applications. The speed and performance of multiplier is among the efficiency improvement parameters of any digital hardware design. Another important feature of hardware designs is self-testing ability. The built-in-self test (BIST) feature helps in quick diagnosis of the hardware functional authenticity. A low power Test Pattern Generator (TPG) is involved in the design for self-test design realization. The low power performance is analyzed with different operating clock frequency and Different FPGA devices with an improvement of around 10% of power with respect to previous design. The designs works at high speed of 3.288Gbps Throughput and 1.5 clock cycle Latency.

Download article

email to a friend

Cite This Article

ISSN: 2349-6002
Volume: 4
Issue: 10
PageNo: 973-979

Simulation of BIST based Multiplier using FPGA

Available:https://ijirt.org/Article?manuscript=145466

23 Oct, 2017

SPEECH QUALITY ENHANCEMENT USING FAST ADAPTIVE KALMAN FILTER

22 Oct, 2017

Driverless Eyes off Road Detection System

13 Oct, 2017

FLOATING-POINT BUTTERFLY ARCHITECTURE BASED ON CARRY SELECT ADDER REPRESENTATION WITH IMPROVEMENT IN SPEED COMPUTATION

05 Sep, 2017

Frequency Reuse of LTE Networks based on RRM

19 Aug, 2017

Power Quality Improvement of PMSG Based DG Set Feeding Three-Phase Loads

17 Aug, 2017

Simulation of An Improved Active Power Filter Performance for Renewable Power Generation systems

17 Aug, 2017

ANALYSIS OF ELECTRIFIED APPLICATION OF TRANSFORMER LESS HYBRID SERIES ACTIVE FILTER.

17 Aug, 2017

A Multilevel Converter With a Floating Bridge for Open-End Winding Motor Drive

17 Aug, 2017

Using modified modulation and double frequency ripple suppression control reduce the capacitance in a single phase PV quasi-z-source inverter

Impact Factor
8.01 (Year 2024)

UGC Approved
Journal no 47859

Join Our IPN

IJIRT Partner Network

Submit your research paper and those of your network (friends, colleagues, or peers) through your IPN account, and receive 800 INR for each paper that gets published.

Join Now

Latest Publication

Recent Conferences

NCSEM 2024

National Conference on Sustainable Engineering and Management - 2024 Last Date: 15th March 2024

Submit inquiry