Design and Implementation of Efficient Floating Point Butter-fly Architecture for Digital Signal Processing

Design and Implementation of Efficient Floating Point Butter-fly Architecture for Digital Signal Processing
Author(s):
M.PRASAD RAO, K.CHINNA MALLA REDDY
Keywords:
FFT Processor, Butterfly unit, DSP, FPGA, VLSI Design.
Abstract
Recently Floating point FFT processor have gained tremendous applications like Radar signal processing, Fast convolution, Spectrum estimation and OFDM based modulators/demodulators. Efficient VLSI based architectures are required for real time signal processing applications. Most of the systems employ DSP processor for these types of computations. The complexity of designing and implementation of Floating-point FFT processor on FPGA is tedious process. It requires large no.of multiply accumulate units to process large number of sampled date. The complex multipliers used in the processor are realized with shift-and-add operations. In this paper we proposed an efficient floating point multiplier and adder to avoid the complexity of designing on VLSI FPGA. The proposed method gives qualitative and quantitative results of 23.87% improvement in delay, 12.50% reduction in power consumption and it requires 29.97% of CPU execution time over the existing methods.
Article Details
Unique Paper ID: 146179 Publication Volume & Issue: Volume 4, Issue 11 Page(s): 2000 - 2008
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