Design and Implementation of BISR for 3d Multiple SRAMS with Redundancies in a SOC

Design and Implementation of BISR for 3d Multiple SRAMS with Redundancies in a SOC
Author(s):
K.Rukiya Begum, S.Lakshmi Kanth Reddy
Keywords:

Abstract
Error correction code (ECC), built-in-self-repair (BISR) techniques by using redundancies has been widely used for improving the yield and reliability of embedded memories. The target faults of these two schemes are soft errors and permanent (hard) faults, respectively. In recent works, there are also some techniques integrating ECC and BISR to deal with soft errors and hard defects simultaneously. However, this will compromise reliability, since some of the ECC protection capability is used for repairing single hard faults. To cure this dilemma, I propose an ECC-enhanced BISR (EBISR) technique, which uses ECC to repair single permanent faults first and spares for the remaining faults in the production/power-ON test and repair stage (PTR). However, techniques are proposed to maintain the original reliability during the online test and repair stage. I also propose the corresponding hardware architecture for the EBISR scheme. A simulator is implemented to evaluate the hardware overhead (HO), repair rate, reliability, and performance penalty. Experimental results show that the proposed EBISR scheme can improve yield and reliability significantly with negligible HO and performance penalty.
Article Details
Unique Paper ID: 147150 Publication Volume & Issue: Volume 5, Issue 5 Page(s): 15 - 21
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