CERTAIN INVESTIGATIONS ON POWER OPTIMIZATION TECHNIQUES FOR MULTIPLIERS IN VLSI
Author(s):
Prerana P. Autade, Dr.Anupama A. Deshpande, Dr.Satish M.Turkane
Keywords:
Multipliers, VSLI Design, Reducing Technique, Power Optimization.
Abstract
In VLSI circuit, space, power consumption, & speed are all significant design considerations. On overall performance of circuits, design component has contradictory effect. Compromises in various components can be used to optimise power dissipation. In VLSI circuits (such as multipliers), power consumption is also data dependent. goal of this study is to compare different design techniques & suggest modular strategy for reducing power usage. It has been discovered that algorithm-based design reduces gate switching activity and, as result, reduces multiplier power consumption. While utilising partly guarded methodology, power consumption is decreased by 10-44 percent with 30-36 percent less area overhead, while using temporal tilling method, array multiplier delay & power dissipation are observed to rise by 50 percent & 30 percent, respectively. Wallace tree multiplier recorded by Booth is determined to be 67% quicker than Wallace tree multiplier, 53% faster than Vedic multiplier, & 22% faster than radix 8 booth multipliers. For Wallace multiplier, bypassing multiplier, modified booth multiplier, & Vedic multiplier, we investigate several optimization approaches. Arithmetic operations, particularly multiplication operations, use significant amount of processing time in conventional processor central processing unit. Multiplication is fundamental mathematical operation that needs significantly more hardware & processing time than addition & subtraction.
Article Details
Unique Paper ID: 153141

Publication Volume & Issue: Volume 8, Issue 5

Page(s): 648 - 652
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