Implementation and Verification of Memory Controller Using System Verilog
Author(s):
Darshan V, Dr. Radha B.L
Keywords:
Abstract
The performance of the memory is the main area of the computer system that needs to be improved. Memory controllers enable efficient data control between the processor and memory. As a result, numerous techniques are being used in modern computer systems by different researchers to enhance memory capacity. One of these initiatives was the introduction of Memory Controllers (MC), a reliable data control intermediary between the processor and memory. Any design path must include verification because it is completed before silicon growth. Thus, we connect ROM, FLASH, SSRAM, and SDRAM to create the memory controller. It is possible to electrically program the memory regulator. A constraint irregular confirmation environment that is inclusion operated and erasable ROM are intended for the planned storage regulator. The code is written in Verilog HDL, and Verilog is also used to complete the confirmation. The reproduction is completed, and inclusion results are obtained, using the QuestaSim 10.0b programming tool. Our method's confirmation climate achieves a utilitarian inclusion of 96.8%, a declaration success of 100%, and zero percent statement disappointments. Reproduction results show that the intended regulator performed well and complied with all framework requirements.
Article Details
Unique Paper ID: 156382

Publication Volume & Issue: Volume 9, Issue 3

Page(s): 876 - 881
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