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DESIGN OF POWER AND AREA OF EFFICIENT APPROXIMATE MULTIPLIERS

  • Unique Paper ID: 157533
  • Volume: 9
  • Issue: 7
  • PageNo: 474-478
  • Abstract:
  • Energy consumption has become one of the most critical design challenges in integrated circuit design. Arithmetic computing circuits, in particular array-based arithmetic computing circuits such as adders, multipliers, squarer’s, have been widely used. Hence, reduction of energy consumption of array- based arithmetic computing circuits is an important design consideration. To this end, designing low-power arithmetic circuits by intelligently trading off processing precision for energy saving in error-resilient applications such as DSP, machine learning and neuromorphic circuits provides a promising solution to the energy dissipation challenge of such systems. To solve the chip’s energy problem, especially for those applications with inherent error resilience, array-based approximate Multipliers circuits (AAMC) circuits that produce errors while having improved energy efficiency have been proposed.
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Cite This Article

  • ISSN: 2349-6002
  • Volume: 9
  • Issue: 7
  • PageNo: 474-478

DESIGN OF POWER AND AREA OF EFFICIENT APPROXIMATE MULTIPLIERS

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