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DESIGN AND IMPLEMENTATION OF I2C SINGLE MASTER ON FPGA USING VERILOG

  • Unique Paper ID: 160766
  • Volume: 10
  • Issue: 1
  • PageNo: 1222-1226
  • Abstract:
  • Design of the I2C single master, consists of a bidirectional data line, serial data line (SDA), and serial clock line. The protocol presented may accommodate several masters. The I2C serial bus, which has two wires and is bidirectional, enables rapid device-to-device communication without compromising data integrity. It is a quick and efficient method of sending data between devices. Other bus protocols require extra pins and signals to link devices, whereas it can operate a network of device chips using just two general-purpose I/O pins. It only requires two lines for communication with two or more chips. Model SIM is used to duplicate the entire Verilog-written module in a smaller number of I2C devices. The strength of the I2C protocol is in its innate ability to employ chip addressing, which makes it simple to add new components to the bus.
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  • ISSN: 2349-6002
  • Volume: 10
  • Issue: 1
  • PageNo: 1222-1226

DESIGN AND IMPLEMENTATION OF I2C SINGLE MASTER ON FPGA USING VERILOG

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