DEVELOPMENT OF AREA-EFFICIENT USING ENCODER DECODER AND EDC FOR 5G LDPC CODES
Author(s):
Agastiya.A, A.Deepalakshmi M.E
Keywords:
Low-density parity-check codes, 5G LDPC decoder, high-performance, VLSI implementation.
Abstract
The fifth-generation (5G) new radio has used the low-density parity-check (LDPC) code as a highly promising error-correction code as the channel coding scheme. However, designing a high-performance decoder for 5G LDPC codes is extremely difficult since their intrinsic multiple degree-1 variable-nodes are prone to error. The problem is handled elegantly in this study by introducing a low-complexity check-node update algorithm, which considerably improves the dependability of check-to-variable messages. By implementing the proposed column degree modification approach, our decoder might outperform existing ones by 0.4dB. This research also provides an efficient 5G LDPC decoder design. Layer merging, split storage mechanism, and selective-shift structure are presented to benefit the special structure of 5G LDPC codes, allowing for a considerable decrease in decoding latency and area consumption. The results of implementation using 90-nm CMOS technology show that the suggested decoder architecture achieves an outstanding gain in throughput-to-area ratio, up to 173.3% when compared to traditional design.
Article Details
Unique Paper ID: 161302

Publication Volume & Issue: Volume 10, Issue 3

Page(s): 247 - 253
Article Preview & Download


Share This Article

Join our RMS

Conference Alert

NCSEM 2024

National Conference on Sustainable Engineering and Management - 2024

Last Date: 15th March 2024

Call For Paper

Volume 11 Issue 1

Last Date for paper submitting for Latest Issue is 25 June 2024

About Us

IJIRT.org enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on editor@ijirt.org

Social Media

Google Verified Reviews