Performance Analysis of CMOS NOR and NAND Gate using Sleepy Stack Power Dissipation
Mahima Yadav, Laxmi Narayan Gahalod, Dr. Soni Changlani
NAND Gate, NOR Gate, Sleepy Keeper, CMOS Circuit
In today’s world of consumer electronics there is a requirement of high frequency circuits which is having low power consumption so that it can be used in designing battery driven handheld devices. On the other hand there is a huge requirement of CMOS technology compatible device which can be used as power amplifiers for communication devices like repeaters and routers. NAND and NOR gates were implemented using various technique approaches for digital schematic design such as sleepy keeper, stack approach etc. Power utilization analysis of the various method techniques for NAND and NOR gates were implemented. Finally compared the power utilization analysis for the various techniques of the proposed and existing methods. To Survey the various existing research works that are relevant to the proposed research work such as sleepy stack, dual stack, zigzag, forced stack etc. To analyze the power gating and multi-threshold CMOS circuits, input vector control and data driven clock circuits that are relevant to the proposed research work. To implement and power utilization analysis for both NAND and NOR gates using sleepy keeper approach and comparing with various existing methods.
Article Details
Unique Paper ID: 161543

Publication Volume & Issue: Volume 10, Issue 4

Page(s): 552 - 556
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