A Review Of The Design & Implementation Of Efficient Architecture For DFT
Author(s):
Maithreyi, Adarsha B V, Vinay, Harsha B V , Ranjith H D
Keywords:
Discrete Fourier Transform (DFT), Digital Signal Processing (DSP), Verilog HDL, Cadence tools, Fast Fourier Transform (FFT), Computational Complexity, Real-Time Processing, FPGA, ASIC,2-point Radix-2 DIT-FFT, Carry-Save Adders, Booth Multipliers, MAC Unit, Hardware-Efficient Architecture, Software Simulation, Real Values, Bit-Width, Signal Transformation, Specialized Hardware Solutions, Hardware Descriptive Language
Abstract
The Discrete Fourier Transform (DFT) is a critical tool for digital signal processing, used to convert signals from the time domain to the frequency domain. This project aims to design an efficient DFT architecture using Verilog hardware description language and validate it using Cadence tools. Over the years, DFT implementation has evolved significantly. Initially, DFT was performed using general-purpose processors, but the demand for real-time processing has led to the exploration of specialized hardware solutions. The Fast Fourier Transform (FFT) has been a major advancement, reducing computational complexity from O(N^2) to O(N log N). Current trends are focused on making FFT algorithms faster in hardware, such as in Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). This project seeks to capitalize on these advancements by implementing a 2-point radix-2 Decimation-In-Time FFT algorithm. It will utilize sophisticated techniques like carry-save adders and Booth multipliers in its system architecture for improved performance. The project's scope involves designing a 2-point Decimation-In-Time FFT architecture with a bit-width of [3:0] and considering only real values, excluding the imaginary part in the testbench. Cadence tools will be employed to perform software simulation for validation, ensuring accuracy and efficiency. This work aims to provide an efficient hardware solution for real-time applications in the digital signal processing domain, pushing the boundaries of current FFT implementation. The simulation was performed using Cadence tools. The methodology encompasses the design of carry-save adders and booth multipliers, the design of the Multiply-Accumulate (MAC) unit, and the architecture design for DFT.
Article Details
Unique Paper ID: 167185

Publication Volume & Issue: Volume 11, Issue 3

Page(s): 565 - 569
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