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IMPLEMENTATION OF EFFICIENT 4X4 COLUMN BY PASSING MULTIPLIER USING 2:1 MULTIPLEXER BASED ADDER

  • Unique Paper ID: 178413
  • Volume: 11
  • Issue: 12
  • PageNo: 3644-3647
  • Abstract:
  • Multiplication is a basic computation in digital signal processing and VLSI design for which speed, power, and area need to be optimized. An efficient 4×4 Column Bypassing Multiplier implemented with a 2:1 multiplexer-based adder on Tanner EDA is discussed in this paper. Column bypassing saves dynamic power dissipation by bypassing computations, if some of the multiplier bits are zero, thus improving energy efficiency. To further improve performance, a 2:1 multiplexer-based adder is utilized, using fewer transistors and propagation delay than standard adders. The design is simulated in Tanner EDA with CMOS technology, and its performance is compared on the basis of power dissipation, delay, and area usage. Simulation results show that the proposed multiplier architecture has substantial power savings and better computational speed over traditional multipliers and is well suited for low-power VLSI and embedded systems. The method offers a power-efficient and high-speed multiplication solution and opens the door to further energy-constrained digital design optimizations
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Cite This Article

  • ISSN: 2349-6002
  • Volume: 11
  • Issue: 12
  • PageNo: 3644-3647

IMPLEMENTATION OF EFFICIENT 4X4 COLUMN BY PASSING MULTIPLIER USING 2:1 MULTIPLEXER BASED ADDER

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