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@article{143671,
        author = {SHAVEL GUPTA and RAHUL CHAUDHARY and ABHISHEK ANAND and NISHA YADAV},
        title = {COMPARISON ANALYSIS OF HIGH-PERFORMANCE DOMINO OR-GATE LOGIC CIRCUIT DESIGNS FOR HIGH-SPEED APPLICATIONS},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {2},
        number = {12},
        pages = {411-414},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=143671},
        abstract = {Nowadays, Design for low power has become one of the major concerns for complex, very large scale integration (VLSI) circuits. As technology has shrunk to 90nm i.e. tens of millions of gates are implemented on relatively small die, leading to increase in leakage current. Domino logic gates are widely utilized in high performance designs because of their speed. The performance of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage due to which they suffer from high noise sensitivity.  In this paper, we compared several domino logic circuit designs to improve the performance along with leakage power. Lower total power consumption is achieved by utilizing these techniques shown. These Domino logic circuits are simulated in T-SPICE tool.},
        keywords = {Domino logic, High-speed, Leakage current, Power consumption.},
        month = {},
        }