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@article{173547,
        author = {Venkatesh V and Y. Sai Rahul and Vipul Pyati and Vishal Patil and Dr. Kumar P},
        title = {UVM Based Design and Verification of AHB to APB Protocol},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {10},
        pages = {724-728},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=173547},
        abstract = {The project focuses on the design and verification of a bridge protocol that connects the AHB (Advanced High- performance Bus) to the APB (Advanced Peripheral Bus) using UVM (Universal Verification Methodology). It aims to create a reliable interface between these two commonly used bus architectures. The design process includes implementing the bridge log ic in UVM, addressing critical elements such as data transfer, address mapping, and control signals. Various verification techniques, such as simulation and testing, are employed to ensure the bridge protocol’s accuracy and reliability. The AHB to APB bridge plays a crucial role in integrating different bus protocols and enabling efficient communication between high- performance processing units and slower peripherals, contributing to the overall effectiveness and functionality of the SoC. This work focuses on functional verification of AMBA AHB to APB Bridge protocol for completeness by employing System Verilog layered testbench architecture. This ensures complete verification of functionality with maximal coverage.},
        keywords = {AMBA, VLSI, VIP, SoC, APB, UVM, Design Verification.},
        month = {March},
        }