Copyright © 2026 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

@article{174576,
        author = {Dr. Tammisetti Ashok and P. Sekhar and T. Hari Veerendra and T.H.N.N. Sai Ram and S. Hemanth Kumar and Y. Lokeswar Satya},
        title = {VERILOG IMPLEMENTATION FOR IMAGE ENCRYTION AND DECRYPTION USING THE ASYMMETRIC RSA ALGORITHM},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {11},
        pages = {21-27},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=174576},
        abstract = {This work offers Verilog's asymmetric RSA algorithm image encryption and decryption implementation to improve digital image security in communication systems. Using a public key, the RSA method encrypts image pixel values; subsequently, it decodes them with a private key so guaranteeing secrecy. Using parallel processing and pipelining to maximize encryption and decryption operations, the hardware-efficient design made possible by Verilog—a hardware description language—is Image pixels are first turned into numerical data, then subjected to RSA encryption either pixel- or block-level, and then rebuilt during decryption. Verilog's modularity makes scalable, customizable encryption circuits fit for many image sizes and resolutions possible. This hardware-based approach provides a robust and efficient solution for secure image transmission, cloud storage, and digital watermarking, demonstrating the potential of FPGA-based encryption in improving security and performance in embedded systems},
        keywords = {FPGA. RSA algorithm, Encryption, Description},
        month = {March},
        }