Copyright © 2026 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

@article{198706,
        author = {M. Jhansi Rani and P. Bhavani and P. Sanjay and N. Bharath Reddy and P. Anantha Raghavan},
        title = {Design & Verification Of 16-bit RISC Processor Using Vedic Mathematics},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {9928-9932},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=198706},
        abstract = {The rapid advancement of digital systems demands processors that are not only fast but also efficient in terms of power and hardware utilization. This work presents the design and verification of a 16-bit Reduced Instruction Set Computing (RISC) processor enhanced with Vedic mathematics techniques. RISC architecture is known for its simplified instruction set, enabling faster execution and easier pipelining. In this design, Vedic mathematical algorithms, particularly from ancient Indian computation methods, are incorporated into the Arithmetic Logic Unit (ALU) to improve arithmetic performance. The processor is model using hardware description language and verified through simulation tools to ensure functional correctness. The proposed approach demonstrates improvements in speed and computational efficiency while maintaining a compact hardware footprint. This makes it suitable for embedded systems and real-time applications where performance and resource optimization are critical.},
        keywords = {16-bit RISC Processor, Vedic Mathematics, ALU, FPGA, HDL, Processor Design, Verification, Embedded Systems.},
        month = {April},
        }