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@article{199126,
        author = {K. Jagadesh Reddy and J. Chandravally and G. Yashwanthi and J. Gnaneshwar and E. Prabhakar},
        title = {Design and Simulation Of 16-Bit Pipelined RISC Processor},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {12414-12419},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=199126},
        abstract = {The design of efficient processor architectures is essential for improving performance in modern digital systems. A basic single-cycle 16-bit RISC processor executes one instruction per clock cycle but suffers from low throughput due to long critical paths and inefficient hardware utilization. To address these limitations, this paper presents the design and implementation of a 16-bit pipelined RISC processor based on Harvard architecture. The proposed design employs a 5-stage pipeline consisting of Instruction Fetch, Decode, Execute, Memory Access, and Write Back stages, enabling parallel execution of multiple instructions. Hazard detection and forwarding units are incorporated to handle data and control hazards effectively, ensuring correct execution with minimal performance loss. The processor is modeled using Verilog HDL, verified through simulation, and synthesized using FPGA tools. The results demonstrate improved instruction throughput and efficient resource utilization compared to single-cycle architectures, making the design suitable for embedded and educational applications.},
        keywords = {RISC Processor, Pipelining, Harvard Architecture, Hazard Detection, Forwarding Unit, Verilog HDL, Embed-ded Systems.},
        month = {April},
        }