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@article{200986,
        author = {Jai Aditya T and Dhivya G B and Sasmitha S P and Abirami S A and Mr. Manokaran J},
        title = {RTL-Based Design and Simulation of a Hardware CNN Accelerator Using Verilog and Python},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {12},
        pages = {3650-3655},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=200986},
        abstract = {Convolutional Neural Networks (CNNs) have become one of the most widely used computational models in modern image processing and computer vision due to their ability to extract meaningful spatial features from input images. CNNs are applied in a broad range of fields including image classification, medical diagnosis, surveillance, object detection, robotics, and edge AI systems. However, the convolution operation that forms the core of CNN computation involves a large number of repetitive multiply and accumulate operations over the input feature map. When these operations are executed sequentially on a conventional processor, the result is high execution latency, increased memory access overhead, and reduced energy efficiency. These limitations motivate the need for hardware-aware computation models that can map convolution into efficient parallel structures.
This paper presents the design and simulation of a hardware-aware CNN accelerator using both Python and Verilog HDL. The work adopts a hybrid methodology in which convolution is first demonstrated in software using grayscale image inputs and multiple filter kernels, followed by a hardware-oriented implementation using Multiply-Accumulate (MAC) based design. In the software domain, convolution is performed using a traditional loop-based method and an optimized computation method in order to compare performance and validate correctness. Edge detection and sharpening filters are applied to generate feature maps and observe the effect of kernel-based image transformation. The results show that the optimized method reduces execution time while preserving output correctness, thereby illustrating the advantage of computation-efficient design.
In the hardware domain, the same convolution concept is mapped into RTL using Verilog HDL. A MAC unit is designed as the fundamental arithmetic block, and a 3×3 convolution module is constructed by combining multiple MAC operations. The hardware design is synthesized and analysed using Intel Quartus II, and the RTL viewer is used to verify the structural representation of multipliers, adders, and registers. The implementation demonstrates how convolution operations can be translated into hardware-efficient structures suitable for CNN accelerator design. The proposed work provides a practical understanding of software-to-hardware mapping and offers a foundation for future development of VLSI-based AI accelerators.},
        keywords = {Convolutional Neural Networks, CNN Accelerator, Hardware-Aware Design, Multiply-Accumulate Unit, Verilog HDL, RTL Design, Quartus II, Image Processing, Edge AI},
        month = {May},
        }