Copyright © 2026 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
@article{204408,
author = {K. L. Manogna and Swathi .p and Ch Poornima and Bhavana Reddy.onteddu and Ramagiri Siddaiah},
title = {Real-Time Implementation of a Pong Game on FPGA Using Verilog HDL and VGA Display Interface},
journal = {International Journal of Innovative Research in Technology},
year = {2026},
volume = {13},
number = {1},
pages = {4745-4751},
issn = {2349-6002},
url = {https://ijirt.org/article?manuscript=204408},
abstract = {This paper presents the design, simulation, and real-time implementation of a classic Pong video game on a Field Programmable Gate Array (FPGA) using Verilog Hardware Description Language (HDL) and a VGA display interface. The system was implemented on the Digilent Nexys 4 DDR board, which integrates a Xilinx Artix-7 FPGA operating at a 100 MHz clock frequency. The primary objective was to develop a fully functional real-time gaming environment without the use of any processor or external software, thereby demonstrating the capability of reconfigurable hardware for embedded graphical applications.
The Pong game architecture includes a frame generator, VGA timing controller, pixel mapper, ball motion logic, paddle controller, collision detection engine, and score tracking module. The VGA controller complies with the 640×480 at 60 Hz standard and manages horizontal and vertical synchronization pulses in accordance with VESA guidelines. Game logic is implemented using Finite State Machines (FSMs) to handle paddle movement through onboard push buttons, ball bouncing mechanics, and scoring transitions. All display elements — the ball, paddles, and score boundaries — are rendered dynamically at the pixel level in synchronization with the active display region.
Functional simulation in Vivado confirmed FSM state transitions, timing accuracy, and output synchronization. Hardware validation on the Nexys 4 DDR board demonstrated stable gameplay with a 60 Hz compliant refresh rate and minimal input latency. The results validate the suitability of FPGAs as real-time graphics engines for interactive embedded systems, with potential extensions including AI-driven paddle control, in-game customization via switches, and HDMI display adaptation.},
keywords = {FPGA, Pong Game, Verilog HDL, Real-Time Display, VGA Controller, Finite State Machine, Nexys 4 DDR, Collision Detection.},
month = {June},
}
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