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@article{204453,
        author = {Charugundla Midhun Sri Gupta and Avanigadda Jayasurya and LAVETI ABHI and Merugumalli Anant Krishna and SAAJIBILLI PRUDHVI RAJ},
        title = {Design and Implementation of UART Communication Protocol on FPGA Using Verilog HDL},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {1},
        pages = {3185-3195},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=204453},
        abstract = {Universal Asynchronous Receiver Transmitter (UART) is one of the most widely employed serial communication protocols in embedded systems, field-programmable gate arrays (FPGAs), and digital electronics owing to its simplicity, minimal pin requirements, and robust long-distance communication capability. This paper presents the design, Verilog HDL implementation, synthesis, and hardware verification of a complete UART communication system on the AMD Artix-7 Nexys A7 FPGA development board. The proposed system operates with a 100 MHz onboard clock and communicates at a standard baud rate of 9600 bps. The UART transmitter serializes 8-bit parallel data supplied through the board’s slide switches (SW [7:0]) and transmits it over the TX line upon assertion of a debounced push-button signal. The UART receiver incorporates a two-flip-flop synchronizer and mid-bit sampling strategy to reconstruct the incoming serial byte robustly. The reconstructed parallel data is displayed on the eight onboard LEDs, and the transmitted character simultaneously appears on a PC serial monitor via the USB–UART bridge. Synthesis and implementation are carried out using Xilinx Vivado Design Suite, with all timing constraints satisfied under static timing analysis. Experimental results con- firm error-free ASCII character transmission and reception at 9600 bps, accurate binary LED output, and correct RTL schematic generation. The modular Verilog architecture is resource efficient and directly extensible to higher baud rates, parity checking, FIFO buffering, and multi-channel UART systems for IoT and industrial embedded applications.},
        keywords = {FPGA, UART, Serial Communication, Verilog HDL, Baud Rate Generation, Nexys A7, Artix-7, Embedded Systems, RTL Synthesis, Vivado},
        month = {June},
        }